1. Field of the Invention
Embodiments of the present invention relate generally to memory devices and, more specifically, in one or more embodiments, to methods of operating floating-gate memory devices to reduce problems associated with over-programmed memory cells.
2. Description of the Related Art
Processor-based systems, such as computers, typically include one or more memory devices to provide storage capability for the system. System memory is generally provided in the form of one or more devices (e.g., integrated circuit chips) and generally includes both random access memory (RAM) and read-only memory (ROM). System RAM is typically large and volatile and provides the system's main memory. Static RAM and Dynamic RAM are commonly employed types of random access memory. In contrast, system ROM is generally small and includes non-volatile memory for storing initialization routines and identification information. Electrically erasable read-only memory (EEPROM) is one commonly employed type of read-only memory, wherein an electrical charge may be used to program and/or erase data in the memory.
One type of non-volatile memory that is of particular use is a flash memory. A flash memory is a type of EEPROM that can be erased and reprogrammed in blocks. Flash memory is often employed in personal computer systems in order to store the Basic Input Output System (BIOS) program such that it can be easily updated. Flash memory is also employed in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized and to provide the ability to remotely upgrade the device for enhanced features.
A typical flash memory includes a memory array having a large number of memory cells arranged in rows and columns. The memory cells are generally grouped into blocks such that groups of cells can be programmed or erased simultaneously. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. Floating-gate memory cells differ from standard MOSFET designs in that they include an electrically isolated gate, referred to as the “floating gate,” in addition to the standard control gate. The floating gate is generally formed over the channel and separated from the channel by a gate oxide. The control gate is formed directly above the floating gate and is separated from the floating gate by another dielectric layer. A floating-gate memory cell stores information by holding electrical charge within the floating gate. By adding or removing charge from the floating gate, the threshold voltage of the cell changes, thereby defining whether this memory cell is programmed or erased.
A NAND flash-memory device is a common type of flash-memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash-memory devices is arranged such that the control gate of each memory cell of a row of the array is connected to a “word” line. Columns of the array include strings (often termed “NAND strings”) of memory cells connected together in series, source to drain, between a pair of select lines, a source select line and a drain select line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. The select gates are typically field-effect transistors. Each source select gate is connected to a source line, while each drain select gate is connected to a column “bit” line.
In operation, the word lines select the individual memory cells to be programmed or read from and operate the unselected memory cells of each string as pass transistors. In a typical programming operation, a gate programming voltage is applied to the word line connected to a control gate of the memory cell to be programmed. In addition, a program pass-through voltage is applied to the word lines connected to the control gates of unselected memory cells, so that they pass current in a manner that is unrestricted by their stored data values. To determine whether the target memory cell has been programmed to the desired state, a program-verify operation is then performed. In a typical program-verify operation, a read voltage is applied to the word line connected to the control gate of the selected memory cell. In addition, a verify pass-through voltage is applied to the word lines connected to the control gates of the unselected memory cells, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each NAND string via the corresponding select gates, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines.
Over-programming of a memory cell may occur when the threshold voltage of the memory cell goes too high. For floating-gate memory cells in particular, over-programming is generally undesirable. For instance, in program-verify operations, a pass-through voltage is applied to the control gates of unselected memory cells, so that they pass current in a manner that is unrestricted by their stored data values. However, due to its high threshold voltage, an over-programmed cell may not pass current in a manner unrestricted by its stored data value. Accordingly, the entire string containing the over-programmed cell may become non-conductive, preventing the programming of additional cells on that string and potentially resulting in a false verify being returned. In addition, if the threshold voltage of the over-programmed cell drops over time, then the threshold voltage of other cells on the same string would also appear to drop potentially causing read failures.
Embodiments of the present invention may be directed to one or more of the problems set forth above.